| Address | Name | Width | Meaning |
| 4000.0088 | DRAM_MODE_BK0 | w | Bank0 DRAM mode command register
(write) address bits set: 4 bit burst, interleave, latency=2 (read) forces a precharge; used to wake up DRAM at power up |
| 4000.4088 | DRAM_MODE_BK1 | w | Bank1 DRAM mode command register |
| 4000.8088 | DRAM_MODE_BK2 | w | Bank2 DRAM mode command register |
| 4000.C088 | DRAM_MODE_BK3 | w | Bank3 DRAM mode command register |