This document describes the behaviour of a big-endian ARM.
Byte 0 of the memory connected to D[31:24]
Byte 1 of the memory connected to D[23:16]
Byte 2 of the memory connected to D[15:8]
Byte 3 of the memory connected to D[7:0]
Note: The processor may be configured to generate a fault if a non word-aligned address is used during a data transfer operation.
A byte store (STRB) repeats the bottom 8 bits of the source register four times across the data bus. If the byte store is word-aligned, the external memory system should write D[31:24] into byte 0 of the word in memory; if the address is a word address plus one byte, D[23:16] should be written into byte 1 of the word in memory, and so on.
A word load (LDR) should generate a word-aligned address. An address offset from a word boundary by 0 or 2 bytes (halfword alignment) will cause the data to be rotated into the register so that the addressed byte occupies bits 31 to 24. (An address offset from a word boundary by 1 or 3 bytes will cause the data to be rotated into the register so that the addressed byte occupies bits 15 to 8).
A word store (STR) should generate a word-aligned address. The data written to memory are always presented exactly as they appear in the register (ie. Bit 31 of the register appears on D[31]).
Registers: R0 =&76543210 R1 =&00000001 R2 =&00000002 R3 =&00000003 R4 =&00000004 R10=&00001000 R11=&00001004
STR R0,[R10] STRB R1,[R11,#0] STRB R2,[R11,#1] STRB R3,[R11,#2] STRB R4,[R11,#3]
Registers: R0 =&76543210 R1 =&00000001 R2 =&00000002 R3 =&00000003 R4 =&00000004 . . . R10=&00001000 R11=&00001004
Registers: R0 =&FFFFFFFF R1 =&FFFFFFFF R2 =&FFFFFFFF R3 =&FFFFFFFF R4 =&FFFFFFFF R5 =&FFFFFFFF R6 =&FFFFFFFF R7 =&FFFFFFFF . . . R10=&00001000
LDR R0,[R10,#0] ;word-aligned load LDR R1,[R10,#1] LDR R2,[R10,#2] ;halfword-aligned load LDR R3,[R10,#3] LDRB R4,[R10,#0] LDRB R5,[R10,#1] LDRB R2,[R10,#2] LDRB R7,[R10,#3]
Registers: R0=&AABBCCDD R1=&DDAABBCC R2=&CCDDAABB R3=&BBCCDDAA R4=&000000AA R5=&000000BB R6=&000000CC R7=&000000DD . . . R10=&00001000
A byte swap (SWPB) expects the read data on D[31:24] if the supplied address is on a word boundary, on D[23:16] if it is a word address plus one byte, and so on. The selected byte is placed in the bottom 8 bits of the destination register, and the remaining bits of the register are filled with zeros. The byte to be written is repeated four times across the data bus. The external memory system should activate the appropriate byte subsystem to store the data (see description of the single byte write operation).
A word swap (SWP) should generate a word-aligned address. An address offset from a word boundary by 0 or 2 bytes (halfword alignment) will cause the data read from memory to be rotated into the register so that the addressed byte occupies bits 31 to 24.)An address offset from a word boundary by 1 or 3 bytes will cause the data read to be rotated into the register so that the addressed byte occupies bits 15 to 8). The data written to memory are always presented exactly as they appear in the register (ie. Bit 31 of the register appears on D[31]).